mockturtle
stable
  • Getting started
    • Compilation requirements
    • Using mockturtle as a stand-alone tool
    • Using mockturtle as a library in another project
    • Building tests
  • Debugging toolset
    • Testcase minimizer
    • Fuzz testing
    • Debugging utilities
    • Visualization
      • Drawing a figure
      • Printing method
    • Time machine
  • Change Log
    • v0.4 (not yet released)
    • v0.3 (July 12, 2022)
    • v0.2 (February 16, 2021)
    • v0.1 (March 31, 2019)
  • Acknowledgments

Standard library

  • The mockturtle philosophy
  • Network interface API
    • Mandatory types and constants
    • Constructors and copy assignment
    • Methods
      • Duplicate network
      • Primary I/O and constants
      • Create unary functions
      • Create binary functions
      • Create ternary functions
      • Create nary functions
      • Create arbitrary functions
      • Restructuring
      • Structural properties
      • Functional properties
      • Nodes and signals
      • Node and signal iterators
      • Simulate values
      • Mapping
      • Custom node values
      • Visited flags
      • General methods
  • Network Implementations
  • Views
    • topo_view: Ensure topological order
    • depth_view: Compute levels and depth
    • mapping_view: Add mapping interface methods
    • cut_view: Network view on a single rooted cut
    • mffc_view: Network view on a (M)FFC
    • immutable_view: Prevent network changes
    • fanout_view: Compute fanout
    • window_view: Network view on a window
    • binding_view: Add bindings to a technology library
    • names_view: Assign names to signals and outputs
    • cnf_view: Creates a CNF while creating a network
    • color_view: Manages traversal IDs
  • Network events

Algorithms

  • Decomposition
    • DSD decomposition
    • Shannon and Davio decomposition
    • Bi-decomposition
  • Network information extraction
    • Network simulation
      • Simulators
      • Partial simulation
    • Simulation pattern generation
      • Parameters and statistics
      • Algorithm
    • Don’t cares
    • Cut enumeration
      • Parameters
      • Return value
      • Algorithm
      • Pre-defined cut types
      • Special-purpose implementations
    • Reconvergence-driven cuts
    • Extract linear subcircuit
  • Logic restructuring and optimization
    • Akers synthesis
    • Logic resynthesis
    • Resynthesize linear circuit
    • Cut rewriting
      • Parameters and statistics
      • Algorithm
      • Rewriting functions
    • MIG algebraic rewriting
      • Parameters
      • Algorithm
    • Resubstitution
      • Parameters and statistics
      • Structure
      • Detailed statistics
    • Various XAG optimization algorithms
    • Various XMG optimization algorithms
    • Functional reduction
      • Parameters and statistics
      • Algorithm
    • Refactoring
      • Parameters and statistics
      • Algorithm
      • Rewriting functions
    • Balancing
      • Parameters and Statistics
      • Algorithm
      • Rebalancing engines
  • Network transformation and mapping
    • Technology mapping and network conversion
    • LUT mapping
      • Dynamic-programming based heuristic
      • SAT-based mapping
    • Collapse mapped network
    • Node resynthesis
      • Parameters and statistics
      • Algorithm
      • Resynthesis functions
    • k-LUT to graph conversion
      • Algorithm
    • COVER to graph conversion
    • Gate-based network to node-based network
      • Algorithm
    • Cleanup networks
    • Transformations based on equivalence classes
      • Algorithms
    • AQFP buffer insertion and verification
      • Technology assumptions
      • Buffer insertion algorithms
      • Parameters
      • Buffered network data structure
      • Verification of buffered networks
      • Simulation of buffered networks
  • Validation and verification
    • Functional equivalence of circuit nodes
    • CNF generation
    • Miter generation
    • Equivalence checking
      • Parameters and statistics
      • Algorithm

Input/Output

  • Lorina readers
  • Write into file formats
    • Write into AIGER files
    • Write into BENCH files
    • Write into BLIF files
    • Write into structural Verilog files
    • Write into DIMACS files (CNF)
    • Write into DOT files (Graphviz)
    • Write simulation patterns into file

Generators

  • Arithmetic networks
    • Addition and Subtraction
  • Control logic
  • Majority-n networks
  • Modular arithmetic networks
    • Addition and Subtraction
    • Multiplication
    • Utility functions

Properties

  • Properties
    • MIG-based costs
    • Multiplicative complexity costs

Utilities

  • Utility data structures
    • Truth table cache
    • Node map
    • Tech Library
    • Exact Library
    • Supergates utils
    • Cuts
    • Cut sets
    • Index List
    • Stopwatch
    • Progress bar
  • Utility functions
    • Manipulate windows with network data types
mockturtle
  • Docs »
  • Validation and verification
  • Edit on GitHub

Validation and verification¶

  • Functional equivalence of circuit nodes
  • CNF generation
  • Miter generation
  • Equivalence checking
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